tcm_0a@ffe00000 { compatible = "xilinx,tcm-v1.0"; reg = <0x0 0xffe00000 0x0 0x10000>; pnode-id = <0xf>; status = "okay"; }; tcm_1a@ffe20000 { compatible = "xilinx,tcm-v1.0"; reg = <0x0 0xffe20000 0x0 0x10000>; pnode-id = <0x10>; status = "okay"; }; zynqmp_ipi@0 { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 29 4>; xlnx,ipi-id = <7>; #address-cells = <1>; #size-cells = <1>; ranges; /* APU<->RPU0 IPI mailbox controller */ ipi_mailbox_rpu0: mailbox@ff90000 { reg = <0xff990600 0x20>, <0xff990620 0x20>, <0xff9900c0 0x20>, <0xff9900e0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; domains { #address-cells = <0x2>; #size-cells = <0x2>; resource_group: resource_group@0 { compatible = "openamp,remoteproc-v1", "openamp,group-v1"; memory = <0x0 0x3ed40000 0x0 0x4000 0x0 0x3ed44000 0x0 0x4000 0x0 0x3ed48000 0x0 0x100000 0x0 0x3ed00000 0x0 0x40000>; access = <&tcm_0_a 0x0>, <&tcm_0_b 0x0>,; }; openamp_a53 { compatible = "openamp,domain-v1"; #address-cells = <0x2>; #size-cells = <0x2>; memory = <0x0 0x80000000 0x0 0x78000000 0x8 0x0 0x0 0x80000000>; /* * Cluster | cpus-mask | execution-mode * * execution mode for ARM-A CPUs: * 0x0: EL0 * 0x1: EL1 * 0x2: EL2 * 0x3: EL3 * bit 31: secure mode / normal mode (secure mode == 1) */ cpus = <&cpus_a53 0xf 0x2>; /* * Flags field, mapping specific * * memory and reserved-memory: * bit 0: 0/1: RO/RW * * xlnx,zynqmp-ipi-mailbox: * 4 bits for each IPI channel to pass special flags * 0-3 bits: channel 0 * 4-7 bits: channel 1 * 8-11 bits: channel 2 * 12-15 bits: channel 3 * each 4 bits: * bit 0: enable/disable (enable==1) * bit 1: TX/RX (TX==1) * bit 2-3: unused * * Other cases: unused * */ access = <&ipi_mailbox_rpu0 0x13>; /* 0x1: master */ include = <&resource_group 0x1>; }; openamp_r5 { compatible = "openamp,domain-v1"; #address-cells = <0x2>; #size-cells = <0x2>; memory = <0x0 0x0 0x0 0x20000000>; /* * Cluster | cpus-mask | execution-mode * * execution mode ARM-R CPUs: * bit 30: lockstep (lockstep enabled == 1) * bit 31: secure mode / normal mode (secure mode == 1) */ cpus = <&cpus_r5 0x2 0x80000000>; /* 0x0: slave */ include = <&resource_group 0x0>; }; };