Following up on my action to send out a block diagram to show interconnects and bus firewalls.

Let's refer to the Technical Reference Manual of the Xilinx Versal board: https://www.xilinx.com/support/documentation/architecture-manuals/am011-vers...

If you look for "Figure 3" at page 44 you can see a diagram representing the interconnects. It also marks the XMPU and XPPU. XMPU and XPPU are the two "bus firewalls" that we have. For more information on the XMPU, see page 280.

I hope this helps. Rob, if you have any specific questions I'll try to address them.

On Tue, 17 Nov 2020, Nathalie Chan King Choy via System-dt wrote:

Hi all,

Action items to complete prior to the call:

·        Stefano & Loic: send the block diagrams of ST & Xilinx systems to the System DT mailing list

·        Stefano: Kick off discussion on aligning the remote processor bindings

Agenda:

• Stefano, Loic, Rob: Continue discussion on bus firewalls in the context of system block diagrams
• Stefano: Remote processor bindings

Call scheduled based on overlapping availability of the speakers. Will record for those who can’t make it.

Thanks & regards,

Nathalie

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