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[PATCH v8 0/6] Add Xilinx RPU subsystem support

by Tanmay Shah

This patch series adds bindings document for RPU subsystem found on Xilinx ZynqMP platforms. It also adds device nodes and driver to enable RPU subsystem in split mode and lockstep mode. Xilinx ZynqMP platform contains Remote Processing Unit(RPU). RPU subsystem contains two arm cortex r5f cores. RPU subsystem can be configured in split mode, lockstep mode and single-cpu mode. RPU subsystem also contains 4 Tightly Coupled Memory(TCM) banks. In lockstep mode, all 4 banks are combined and total of 256KB memory is made available to r5 core0. In split mode, both cores can access two TCM banks i.e. 128 KB. RPU can also fetch data and execute instructions from DDR memory along with TCM memory. --- Changes in v8: - add 'items:' for sram property Changes in v7: - Add minItems in sram property Changes in v6: - Add maxItems to sram and memory-region property Changes in v5: - Add constraints of the possible values of xlnx,cluster-mode property - fix description of power-domains property for r5 core - Remove reg, address-cells and size-cells properties as it is not required - Fix description of mboxes property - Add description of each memory-region and remove old .txt binding link reference in the description - Remove optional reg property from r5fss node - Move r5fss node out of axi node Changes in v4: - Add memory-region, mboxes and mbox-names properties in dt-bindings example - Add reserved memory region node and use it in Xilinx dt RPU subsystem node - Remove redundant header files - use dev_err_probe() to report errors during probe - Fix missing check on error code returned by zynqmp_r5_add_rproc_core() - Fix memory leaks all over the driver when resource allocation fails for any core - make cluster mode check only at one place - remove redundant initialization of variable - remove redundant use of of_node_put() - Fix Comment format problem - Assign offset of zynqmp_tcm_banks instead of duplicating it - Add tcm and memory regions rproc carveouts during prepare instead of parse_fw - Remove rproc_mem_entry object from r5_core - Use put_device() and rproc_del() APIs to fix memory leaks - Replace pr_* with dev_*. This was missed in v3, fix now. - Use "GPL" instead of "GPL v2" in MODULE_LICENSE macro. This was reported by checkpatch script. Changes in v3: - Fix checkpatch script indentation warning - Remove unused variable from xilinx remoteproc driver - use C style comments, i.e /*...*/ - Remove redundant debug information which can be derived using /proc/device-tree - Fix multiline comment format - s/"final fot TCM"/"final for TCM" - Function devm_kzalloc() does not return an code on error, just NULL. Remove redundant error check for this function throughout the driver. - Fix RPU mode configuration and add documentation accordingly - Get rid of the indentations to match function documentation style with rest of the driver - Fix memory leak by only using r5_rproc->priv and not replace it with new instance - Use 'i' for the outer loop and 'j' for the inner one as per convention - Remove redundant error and NULL checks throughout the driver - Use devm_kcalloc() when more than one element is required - Add memory-regions carveouts during driver probe instead of parse_fw call This removes redundant copy of reserved_mem object in r5_core structure. - Fix memory leak by using of_node_put() - Fix indentation of tcm_mem_map function args - Remove redundant init of variables - Initialize tcm bank size variable for lockstep mode - Replace u32 with phys_addr_t for variable stroing memory bank address - Add documentation of TCM behavior in lockstep mode - Use dev_get_drvdata instead of platform driver API - Remove info level messages - Fix checkpatch.pl warnings - Add documentation for the Xilinx r5f platform to understand driver design Changes in v2: - Remove proprietary copyright footer from cover letter Ben Levinsky (3): firmware: xilinx: Add ZynqMP firmware ioctl enums for RPU configuration. firmware: xilinx: Add shutdown/wakeup APIs firmware: xilinx: Add RPU configuration APIs Tanmay Shah (3): dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings arm64: dts: xilinx: zynqmp: Add RPU subsystem device node drivers: remoteproc: Add Xilinx r5 remoteproc driver .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 132 +++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 33 + drivers/firmware/xilinx/zynqmp.c | 97 ++ drivers/remoteproc/Kconfig | 12 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/xlnx_r5_remoteproc.c | 1045 +++++++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + include/linux/firmware/xlnx-zynqmp.h | 60 + 8 files changed, 1386 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml create mode 100644 drivers/remoteproc/xlnx_r5_remoteproc.c base-commit: 01a1a0c8d456b11f2f6b9b822414481beaa44d6f -- 2.25.1

3 years, 9 months

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Re: [PATCH v6 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings

by Tanmay Shah

On 6/2/22 8:14 AM, Rob Herring wrote: > On Wed, Jun 01, 2022 at 12:05:09PM -0700, Tanmay Shah wrote: >> Hi Rob, >> >> Thanks for reviews. Please find my comments below: >> >> On 6/1/22 11:42 AM, Rob Herring wrote: >>> On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote: >>>> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing >>>> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem >>>> (cluster). >>>> >>>> Signed-off-by: Tanmay Shah <tanmay.shah(a)xilinx.com> >>>> --- >>>> >>>> Changes in v6: >>>> - Add maxItems to sram and memory-region property >>>> >>>> Changes in v5: >>>> - Add constraints of the possible values of xlnx,cluster-mode property >>>> - fix description of power-domains property for r5 core >>>> - Remove reg, address-cells and size-cells properties as it is not required >>>> - Fix description of mboxes property >>>> - Add description of each memory-region and remove old .txt binding link >>>> reference in the description >>>> >>>> Changes in v4: >>>> - Add memory-region, mboxes and mbox-names properties in example >>>> >>>> Changes in v3: >>>> - None >>>> >>>> >>>> .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++++++++++++++++++ >>>> include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + >>>> 2 files changed, 135 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> new file mode 100644 >>>> index 000000000000..cbff1c201a89 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >>>> @@ -0,0 +1,129 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Xilinx R5F processor subsystem >>>> + >>>> +maintainers: >>>> + - Ben Levinsky <ben.levinsky(a)xilinx.com> >>>> + - Tanmay Shah <tanmay.shah(a)xilinx.com> >>>> + >>>> +description: | >>>> + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for >>>> + real-time processing based on the Cortex-R5F processor core from ARM. >>>> + The Cortex-R5F processor implements the Arm v7-R architecture and includes a >>>> + floating-point unit that implements the Arm VFPv3 instruction set. >>>> + >>>> +properties: >>>> + compatible: >>>> + const: xlnx,zynqmp-r5fss >>>> + >>>> + xlnx,cluster-mode: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: [0, 1, 2] >>>> + description: | >>>> + The RPU MPCore can operate in split mode(Dual-processor performance), Safety >>>> + lock-step mode(Both RPU cores execute the same code in lock-step, >>>> + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while >>>> + core 1 runs normally). The processor does not support dynamic configuration. >>>> + Switching between modes is only permitted immediately after a processor reset. >>>> + If set to 1 then lockstep mode and if 0 then split mode. >>>> + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. >>>> + >>>> +patternProperties: >>>> + "^r5f-[a-f0-9]+$": >>>> + type: object >>>> + description: | >>>> + The RPU is located in the Low Power Domain of the Processor Subsystem. >>>> + Each processor includes separate L1 instruction and data caches and >>>> + tightly coupled memories (TCM). System memory is cacheable, but the TCM >>>> + memory space is non-cacheable. >>>> + >>>> + Each RPU contains one 64KB memory and two 32KB memories that >>>> + are accessed via the TCM A and B port interfaces, for a total of 128KB >>>> + per processor. In lock-step mode, the processor has access to 256KB of >>>> + TCM memory. >>>> + >>>> + properties: >>>> + compatible: >>>> + const: xlnx,zynqmp-r5f >>>> + >>>> + power-domains: >>>> + description: RPU core PM domain specifier >>>> + maxItems: 1 >>>> + >>>> + mboxes: >>>> + minItems: 1 >>>> + items: >>>> + - description: mailbox channel to send data to RPU >>>> + - description: mailbox channel to receive data from RPU >>>> + >>>> + mbox-names: >>>> + minItems: 1 >>>> + items: >>>> + - const: tx >>>> + - const: rx >>>> + >>>> + sram: >>>> + $ref: /schemas/types.yaml#/definitions/phandle-array >>>> + maxItems: 8 >>> minItems: 1 >>> maxItems: 8 >>> items: >>> maxItems: 1 >> I have posted v7 which adds "minItems: 1". >> >> However, I didn't get items: part. Is it required to have items: now? > Yes. >> Can I add items: part once TCM bindings are posted? > No. > >> I understand that minItems and maxItems under sram property decides how many >> phandles sram can have. >> >> However, maxItems: 1 under items: field what it describes? > 'phandle-array' is really a matrix type because we can have phandles > plus argument cells. So you have to define each of the 1-8 entries is a > single phandle cell (and no arg cells). Thanks for explanation. I will send new revision as suggested. > > Rob

3 years, 9 months

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Re: [PATCH v6 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings

by Tanmay Shah

Hi Rob, Thanks for reviews. Please find my comments below: On 6/1/22 11:42 AM, Rob Herring wrote: > On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote: >> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing >> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem >> (cluster). >> >> Signed-off-by: Tanmay Shah <tanmay.shah(a)xilinx.com> >> --- >> >> Changes in v6: >> - Add maxItems to sram and memory-region property >> >> Changes in v5: >> - Add constraints of the possible values of xlnx,cluster-mode property >> - fix description of power-domains property for r5 core >> - Remove reg, address-cells and size-cells properties as it is not required >> - Fix description of mboxes property >> - Add description of each memory-region and remove old .txt binding link >> reference in the description >> >> Changes in v4: >> - Add memory-region, mboxes and mbox-names properties in example >> >> Changes in v3: >> - None >> >> >> .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++++++++++++++++++ >> include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + >> 2 files changed, 135 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >> >> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >> new file mode 100644 >> index 000000000000..cbff1c201a89 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml >> @@ -0,0 +1,129 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx R5F processor subsystem >> + >> +maintainers: >> + - Ben Levinsky <ben.levinsky(a)xilinx.com> >> + - Tanmay Shah <tanmay.shah(a)xilinx.com> >> + >> +description: | >> + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for >> + real-time processing based on the Cortex-R5F processor core from ARM. >> + The Cortex-R5F processor implements the Arm v7-R architecture and includes a >> + floating-point unit that implements the Arm VFPv3 instruction set. >> + >> +properties: >> + compatible: >> + const: xlnx,zynqmp-r5fss >> + >> + xlnx,cluster-mode: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [0, 1, 2] >> + description: | >> + The RPU MPCore can operate in split mode(Dual-processor performance), Safety >> + lock-step mode(Both RPU cores execute the same code in lock-step, >> + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while >> + core 1 runs normally). The processor does not support dynamic configuration. >> + Switching between modes is only permitted immediately after a processor reset. >> + If set to 1 then lockstep mode and if 0 then split mode. >> + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. >> + >> +patternProperties: >> + "^r5f-[a-f0-9]+$": >> + type: object >> + description: | >> + The RPU is located in the Low Power Domain of the Processor Subsystem. >> + Each processor includes separate L1 instruction and data caches and >> + tightly coupled memories (TCM). System memory is cacheable, but the TCM >> + memory space is non-cacheable. >> + >> + Each RPU contains one 64KB memory and two 32KB memories that >> + are accessed via the TCM A and B port interfaces, for a total of 128KB >> + per processor. In lock-step mode, the processor has access to 256KB of >> + TCM memory. >> + >> + properties: >> + compatible: >> + const: xlnx,zynqmp-r5f >> + >> + power-domains: >> + description: RPU core PM domain specifier >> + maxItems: 1 >> + >> + mboxes: >> + minItems: 1 >> + items: >> + - description: mailbox channel to send data to RPU >> + - description: mailbox channel to receive data from RPU >> + >> + mbox-names: >> + minItems: 1 >> + items: >> + - const: tx >> + - const: rx >> + >> + sram: >> + $ref: /schemas/types.yaml#/definitions/phandle-array >> + maxItems: 8 > minItems: 1 > maxItems: 8 > items: > maxItems: 1 I have posted v7 which adds "minItems: 1". However, I didn't get items: part. Is it required to have items: now? Can I add items: part once TCM bindings are posted? I understand that minItems and maxItems under sram property decides how many phandles sram can have. However, maxItems: 1 under items: field what it describes? Thanks. > >> + description: | >> + phandles to one or more reserved on-chip SRAM regions. Other than TCM, >> + the RPU can execute instructions and access data from, the OCM memory, >> + the main DDR memory, and other system memories. >> + >> + The regions should be defined as child nodes of the respective SRAM >> + node, and should be defined as per the generic bindings in, >> + Documentation/devicetree/bindings/sram/sram.yaml >> + >> + memory-region: >> + description: | >> + List of phandles to the reserved memory regions associated with the >> + remoteproc device. This is variable and describes the memories shared with >> + the remote processor (e.g. remoteproc firmware and carveouts, rpmsg >> + vrings, ...). This reserved memory region will be allocated on DDR memory. >> + minItems: 1 >> + maxItems: 8 >> + items: >> + - description: region used for RPU firmware image section >> + - description: vdev buffer >> + - description: vring0 >> + - description: vring1 >> + additionalItems: true >> + >> + required: >> + - compatible >> + - power-domains >> + >> + unevaluatedProperties: false >> + >> +required: >> + - compatible >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + r5fss: r5fss { >> + compatible = "xlnx,zynqmp-r5fss"; >> + xlnx,cluster-mode = <1>; >> + >> + r5f-0 { >> + compatible = "xlnx,zynqmp-r5f"; >> + power-domains = <&zynqmp_firmware 0x7>; >> + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; >> + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; >> + mbox-names = "tx", "rx"; >> + }; >> + >> + r5f-1 { >> + compatible = "xlnx,zynqmp-r5f"; >> + power-domains = <&zynqmp_firmware 0x8>; >> + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; >> + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; >> + mbox-names = "tx", "rx"; >> + }; >> + }; >> +... >> diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h >> index 0d9a412fd5e0..618024cbb20d 100644 >> --- a/include/dt-bindings/power/xlnx-zynqmp-power.h >> +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h >> @@ -6,6 +6,12 @@ >> #ifndef _DT_BINDINGS_ZYNQMP_POWER_H >> #define _DT_BINDINGS_ZYNQMP_POWER_H >> >> +#define PD_RPU_0 7 >> +#define PD_RPU_1 8 >> +#define PD_R5_0_ATCM 15 >> +#define PD_R5_0_BTCM 16 >> +#define PD_R5_1_ATCM 17 >> +#define PD_R5_1_BTCM 18 >> #define PD_USB_0 22 >> #define PD_USB_1 23 >> #define PD_TTC_0 24 >> -- >> 2.25.1 >> >>

3 years, 9 months

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[PATCH v7 0/6] Add Xilinx RPU subsystem support

by Tanmay Shah

This patch series adds bindings document for RPU subsystem found on Xilinx ZynqMP platforms. It also adds device nodes and driver to enable RPU subsystem in split mode and lockstep mode. Xilinx ZynqMP platform contains Remote Processing Unit(RPU). RPU subsystem contains two arm cortex r5f cores. RPU subsystem can be configured in split mode, lockstep mode and single-cpu mode. RPU subsystem also contains 4 Tightly Coupled Memory(TCM) banks. In lockstep mode, all 4 banks are combined and total of 256KB memory is made available to r5 core0. In split mode, both cores can access two TCM banks i.e. 128 KB. RPU can also fetch data and execute instructions from DDR memory along with TCM memory. --- Changes in v7: - Add minItems in sram property Changes in v6: - Add maxItems to sram and memory-region property Changes in v5: - Add constraints of the possible values of xlnx,cluster-mode property - fix description of power-domains property for r5 core - Remove reg, address-cells and size-cells properties as it is not required - Fix description of mboxes property - Add description of each memory-region and remove old .txt binding link reference in the description - Remove optional reg property from r5fss node - Move r5fss node out of axi node Changes in v4: - Add memory-region, mboxes and mbox-names properties in dt-bindings example - Add reserved memory region node and use it in Xilinx dt RPU subsystem node - Remove redundant header files - use dev_err_probe() to report errors during probe - Fix missing check on error code returned by zynqmp_r5_add_rproc_core() - Fix memory leaks all over the driver when resource allocation fails for any core - make cluster mode check only at one place - remove redundant initialization of variable - remove redundant use of of_node_put() - Fix Comment format problem - Assign offset of zynqmp_tcm_banks instead of duplicating it - Add tcm and memory regions rproc carveouts during prepare instead of parse_fw - Remove rproc_mem_entry object from r5_core - Use put_device() and rproc_del() APIs to fix memory leaks - Replace pr_* with dev_*. This was missed in v3, fix now. - Use "GPL" instead of "GPL v2" in MODULE_LICENSE macro. This was reported by checkpatch script. Changes in v3: - Fix checkpatch script indentation warning - Remove unused variable from xilinx remoteproc driver - use C style comments, i.e /*...*/ - Remove redundant debug information which can be derived using /proc/device-tree - Fix multiline comment format - s/"final fot TCM"/"final for TCM" - Function devm_kzalloc() does not return an code on error, just NULL. Remove redundant error check for this function throughout the driver. - Fix RPU mode configuration and add documentation accordingly - Get rid of the indentations to match function documentation style with rest of the driver - Fix memory leak by only using r5_rproc->priv and not replace it with new instance - Use 'i' for the outer loop and 'j' for the inner one as per convention - Remove redundant error and NULL checks throughout the driver - Use devm_kcalloc() when more than one element is required - Add memory-regions carveouts during driver probe instead of parse_fw call This removes redundant copy of reserved_mem object in r5_core structure. - Fix memory leak by using of_node_put() - Fix indentation of tcm_mem_map function args - Remove redundant init of variables - Initialize tcm bank size variable for lockstep mode - Replace u32 with phys_addr_t for variable stroing memory bank address - Add documentation of TCM behavior in lockstep mode - Use dev_get_drvdata instead of platform driver API - Remove info level messages - Fix checkpatch.pl warnings - Add documentation for the Xilinx r5f platform to understand driver design Changes in v2: - Remove proprietary copyright footer from cover letter Ben Levinsky (3): firmware: xilinx: Add ZynqMP firmware ioctl enums for RPU configuration. firmware: xilinx: Add shutdown/wakeup APIs firmware: xilinx: Add RPU configuration APIs Tanmay Shah (3): dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings arm64: dts: xilinx: zynqmp: Add RPU subsystem device node drivers: remoteproc: Add Xilinx r5 remoteproc driver .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 130 ++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 33 + drivers/firmware/xilinx/zynqmp.c | 97 ++ drivers/remoteproc/Kconfig | 12 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/xlnx_r5_remoteproc.c | 1045 +++++++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + include/linux/firmware/xlnx-zynqmp.h | 60 + 8 files changed, 1384 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml create mode 100644 drivers/remoteproc/xlnx_r5_remoteproc.c base-commit: 01a1a0c8d456b11f2f6b9b822414481beaa44d6f -- 2.25.1

3 years, 9 months

1
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Re: [PATCH v6 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings

by tanmay.shah＠xilinx.com

On 6/1/22 5:22 AM, Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> wrote: > On 01/06/2022 01:43, Tanmay Shah wrote: > > Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing > > Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem > > (cluster). > > > > Signed-off-by: Tanmay Shah <tanmay.shah(a)xilinx.com> > > --- > > > > Changes in v6: > > - Add maxItems to sram and memory-region property > > > > Changes in v5: > > - Add constraints of the possible values of xlnx,cluster-mode property > > - fix description of power-domains property for r5 core > > - Remove reg, address-cells and size-cells properties as it is not required > > - Fix description of mboxes property > > - Add description of each memory-region and remove old .txt binding link > > reference in the description > > > > Changes in v4: > > - Add memory-region, mboxes and mbox-names properties in example > > > > Changes in v3: > > - None > > > > > > .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++++++++++++++++++ > > include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + > > 2 files changed, 135 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > new file mode 100644 > > index 000000000000..cbff1c201a89 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > @@ -0,0 +1,129 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Xilinx R5F processor subsystem > > + > > +maintainers: > > + - Ben Levinsky <ben.levinsky(a)xilinx.com> > > + - Tanmay Shah <tanmay.shah(a)xilinx.com> > > + > > +description: | > > + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for > > + real-time processing based on the Cortex-R5F processor core from ARM. > > + The Cortex-R5F processor implements the Arm v7-R architecture and includes a > > + floating-point unit that implements the Arm VFPv3 instruction set. > > + > > +properties: > > + compatible: > > + const: xlnx,zynqmp-r5fss > > + > > + xlnx,cluster-mode: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + enum: [0, 1, 2] > > + description: | > > + The RPU MPCore can operate in split mode(Dual-processor performance), Safety > > + lock-step mode(Both RPU cores execute the same code in lock-step, > > + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while > > + core 1 runs normally). The processor does not support dynamic configuration. > > + Switching between modes is only permitted immediately after a processor reset. > > + If set to 1 then lockstep mode and if 0 then split mode. > > + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. > > + > > +patternProperties: > > + "^r5f-[a-f0-9]+$": > > + type: object > > + description: | > > + The RPU is located in the Low Power Domain of the Processor Subsystem. > > + Each processor includes separate L1 instruction and data caches and > > + tightly coupled memories (TCM). System memory is cacheable, but the TCM > > + memory space is non-cacheable. > > + > > + Each RPU contains one 64KB memory and two 32KB memories that > > + are accessed via the TCM A and B port interfaces, for a total of 128KB > > + per processor. In lock-step mode, the processor has access to 256KB of > > + TCM memory. > > + > > + properties: > > + compatible: > > + const: xlnx,zynqmp-r5f > > + > > + power-domains: > > + description: RPU core PM domain specifier > > + maxItems: 1 > > + > > + mboxes: > > + minItems: 1 > > + items: > > + - description: mailbox channel to send data to RPU > > + - description: mailbox channel to receive data from RPU > > + > > + mbox-names: > > + minItems: 1 > > + items: > > + - const: tx > > + - const: rx > > + > > + sram: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + maxItems: 8 > > Without minItems, this means maxItems=minItems and previously you had > here "minItems:1", so is it really what you want? > Ok. I misunderstood previous comment here in that case. I thought minIterms will be 1 by default. But, it is not that way. I will fix this in next revision. Thanks. > Anyway rest looks good to me. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> > > Best regards, > Krzysztof >

3 years, 9 months

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[PATCH v6 0/6] Add Xilinx RPU subsystem support

by Tanmay Shah

This patch series adds bindings document for RPU subsystem found on Xilinx ZynqMP platforms. It also adds device nodes and driver to enable RPU subsystem in split mode and lockstep mode. Xilinx ZynqMP platform contains Remote Processing Unit(RPU). RPU subsystem contains two arm cortex r5f cores. RPU subsystem can be configured in split mode, lockstep mode and single-cpu mode. RPU subsystem also contains 4 Tightly Coupled Memory(TCM) banks. In lockstep mode, all 4 banks are combined and total of 256KB memory is made available to r5 core0. In split mode, both cores can access two TCM banks i.e. 128 KB. RPU can also fetch data and execute instructions from DDR memory along with TCM memory. --- Changes in v6: - Add maxItems to sram and memory-region property Changes in v5: - Add constraints of the possible values of xlnx,cluster-mode property - fix description of power-domains property for r5 core - Remove reg, address-cells and size-cells properties as it is not required - Fix description of mboxes property - Add description of each memory-region and remove old .txt binding link reference in the description - Remove optional reg property from r5fss node - Move r5fss node out of axi node Changes in v4: - Add memory-region, mboxes and mbox-names properties in dt-bindings example - Add reserved memory region node and use it in Xilinx dt RPU subsystem node - Remove redundant header files - use dev_err_probe() to report errors during probe - Fix missing check on error code returned by zynqmp_r5_add_rproc_core() - Fix memory leaks all over the driver when resource allocation fails for any core - make cluster mode check only at one place - remove redundant initialization of variable - remove redundant use of of_node_put() - Fix Comment format problem - Assign offset of zynqmp_tcm_banks instead of duplicating it - Add tcm and memory regions rproc carveouts during prepare instead of parse_fw - Remove rproc_mem_entry object from r5_core - Use put_device() and rproc_del() APIs to fix memory leaks - Replace pr_* with dev_*. This was missed in v3, fix now. - Use "GPL" instead of "GPL v2" in MODULE_LICENSE macro. This was reported by checkpatch script. Changes in v3: - Fix checkpatch script indentation warning - Remove unused variable from xilinx remoteproc driver - use C style comments, i.e /*...*/ - Remove redundant debug information which can be derived using /proc/device-tree - Fix multiline comment format - s/"final fot TCM"/"final for TCM" - Function devm_kzalloc() does not return an code on error, just NULL. Remove redundant error check for this function throughout the driver. - Fix RPU mode configuration and add documentation accordingly - Get rid of the indentations to match function documentation style with rest of the driver - Fix memory leak by only using r5_rproc->priv and not replace it with new instance - Use 'i' for the outer loop and 'j' for the inner one as per convention - Remove redundant error and NULL checks throughout the driver - Use devm_kcalloc() when more than one element is required - Add memory-regions carveouts during driver probe instead of parse_fw call This removes redundant copy of reserved_mem object in r5_core structure. - Fix memory leak by using of_node_put() - Fix indentation of tcm_mem_map function args - Remove redundant init of variables - Initialize tcm bank size variable for lockstep mode - Replace u32 with phys_addr_t for variable stroing memory bank address - Add documentation of TCM behavior in lockstep mode - Use dev_get_drvdata instead of platform driver API - Remove info level messages - Fix checkpatch.pl warnings - Add documentation for the Xilinx r5f platform to understand driver design Changes in v2: - Remove proprietary copyright footer from cover letter Ben Levinsky (3): firmware: xilinx: Add ZynqMP firmware ioctl enums for RPU configuration. firmware: xilinx: Add shutdown/wakeup APIs firmware: xilinx: Add RPU configuration APIs Tanmay Shah (3): dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings arm64: dts: xilinx: zynqmp: Add RPU subsystem device node drivers: remoteproc: Add Xilinx r5 remoteproc driver .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 33 + drivers/firmware/xilinx/zynqmp.c | 97 ++ drivers/remoteproc/Kconfig | 12 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/xlnx_r5_remoteproc.c | 1045 +++++++++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + include/linux/firmware/xlnx-zynqmp.h | 60 + 8 files changed, 1383 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml create mode 100644 drivers/remoteproc/xlnx_r5_remoteproc.c base-commit: 01a1a0c8d456b11f2f6b9b822414481beaa44d6f -- 2.25.1

3 years, 9 months

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Calling for agenda: 2022-05-25 OpenAMP System Reference bi-weekly

by Nathalie Chan King Choy

Hi all, Please let us know your agenda topics. Here's what I've collected: * Any updates on Arm's timeframe & requirements for virtio? * Discuss Arnaud's proposal to have pre-integration of Dan's work first before calling meeting with Xiaomi * Individual updates Thanks Arnaud for your update! (below for quick reference) Thanks & regards, Nathalie From: Arnaud POULIQUEN <arnaud.pouliquen(a)st.com> Sent: Tuesday, May 24, 2022 12:40 AM To: Nathalie Chan King Choy <nathalie(a)xilinx.com> Cc: openamp-system-reference(a)lists.openampproject.org Subject: RE: OpenAMP System Reference bi-weekly Hello, I will not be able to join the OpenAMP System Reference meeting this week. My update: * Rpmsg flow control RFC sent: * Linux: https://lore.kernel.org/lkml/20220520082940.2984914-1-arnaud.pouliquen@foss… * OpenAMP: https://github.com/OpenAMP/open-amp/pull/394 * OpenAMP and libmetal: zephyr integration without a fork: Received advice last week, in Zephyr discussion <https://github.com/zephyrproject-rtos/zephyr/discussions/44279> . I tested approach based on git submodule to suppress the OpenAMP libraries copy in zephyr, work fine without impact on openAMP libs. Bill also developed a solution that works. I propose to discuss approaches on discord chat or on next meeting ( Zephyr upstream scope). For short term (Dan's work integration in OpenAMP), the solution proposed by Bill is simpler to implement. As it avoids creating temporary Zephyr open-amp and libmetal modules repos in OpenAMP. Action items: * @Arnaud POULIQUEN<mailto:arnaud.pouliquen@st.com>: Set up call with Bill, Dan & Xiaomi when Dan is back in office about virtio work It seems to me that it would be better to have a pre-integration of Dan's work first and then call a meeting, to discuss the next steps. But we can have a meeting before if requested. Regards, Arnaud -----Original Appointment----- From: Nathalie Chan King Choy <nathalie(a)xilinx.com<mailto:nathalie@xilinx.com>> Sent: jeudi 9 décembre 2021 19:53 To: Nathalie Chan King Choy; Arnaud POULIQUEN; Arun Balaji Kannan; Bill Mills; Milea, Danut Gabriel (Danut); etsam.anjum(a)siemens.com<mailto:etsam.anjum@siemens.com>; jeffrey.hancock(a)siemens.com<mailto:jeffrey.hancock@siemens.com>; Kumar Gala; nathalie-ckc(a)kestrel-omnitech.com<mailto:nathalie-ckc@kestrel-omnitech.com>; paul.sokolovsky(a)linaro.org<mailto:paul.sokolovsky@linaro.org>; Stefano Stabellini; Tanmay Shah; Tom Gall; Tomas Evensen Subject: OpenAMP System Reference bi-weekly When: mercredi 25 mai 2022 09:00-10:00 (UTC-08:00) Pacific Time (US & Canada). Where: https://xilinx.zoom.us/j/96641483296?pwd=c1ZzeGNJQzR4MGdhN2FRT2VVY05WZz09&f… Note: Around the daylight/standard savings time change Europe and North America meetings get out of sync because the time change dates differ Meeting notes: https://github.com/OpenAMP/openamp-system-reference/wiki/OpenAMP-System-Ref… GitHub wiki: https://github.com/OpenAMP/openamp-system-reference/wiki GitHub repo (published stuff) : https://github.com/OpenAMP/openamp-system-reference Google Drive folder (draft stuff): https://drive.google.com/drive/folders/1dJByUkTNPOczMwB5uNUSKSf1mzQbAjQt?us… OpenAMP System Reference mailing list page: https://lists.openampproject.org/mailman/listinfo/openamp-system-reference [https://st2.zoom.us/static/5.2.3509/image/new/ZoomLogo_110_25.png]<https://zoom.us/> Hi there, Nathalie Chan King Choy is inviting you to a scheduled Zoom meeting. Join Zoom Meeting<https://xilinx.zoom.us/j/96641483296?pwd=c1ZzeGNJQzR4MGdhN2FRT2VVY05WZz09&f…> Phone one-tap: US: +19292056099,,96641483296#,,,,,,0#,,0665597535#<tel:+19292056099,,96641483296#,,,,,,0#,,0665597535#> or +16699006833,,96641483296#,,,,,,0#,,0665597535#<tel:+16699006833,,96641483296#,,,,,,0#,,0665597535#> Meeting URL: https://xilinx.zoom.us/j/96641483296?pwd=c1ZzeGNJQzR4MGdhN2FRT2VVY05WZz09&f… Meeting ID: 966 4148 3296 Passcode: u2!%S7xN@9 Join by Telephone For higher quality, dial a number based on your current location. Dial: US: +1 929 205 6099 or +1 669 900 6833 or +1 720 928 9299 or 833 548 0276 (Toll Free) or 833 548 0282 (Toll Free) or 877 853 5257 (Toll Free) or 888 475 4499 (Toll Free) India: +91 406 480 2722 or +91 446 480 2722 or +91 806 480 2722 or +91 80 71 279 440 or +91 116 480 2722 or +91 22 48 798 004 or +91 224 879 8012 or +91 226 480 2722 or +91 22 71 279 525 or 000 800 001 4002 (Toll Free) or 000 800 050 5050 (Toll Free) Ireland: +353 6 163 9031 or +353 1 536 9320 or +353 1 653 3895 or 1800 949 238 (Toll Free) or 1800 901 561 (Toll Free) or 1800 943 965 (Toll Free) Singapore: +65 3158 7288 or +65 3165 1065 or 800 852 6054 (Toll Free) or 1800 407 5602 (Toll Free) or 800 101 3814 (Toll Free) Meeting ID: 966 4148 3296 Passcode: 0665597535 International numbers<https://xilinx.zoom.us/u/arCaT7VIG> Join from a Video Conference room system Meeting ID: 966 4148 3296 Passcode: 0665597535 US: 96641483296(a)global.zoomcrc.com<mailto:96641483296@global.zoomcrc.com> Passcode: 0665597535 APAC: 96641483296(a)global.zoomcrc.com<mailto:96641483296@global.zoomcrc.com> Passcode: 0665597535 India: 96641483296(a)global.zoomcrc.com<mailto:96641483296@global.zoomcrc.com> Passcode: 0665597535 Europe: 96641483296(a)global.zoomcrc.com<mailto:96641483296@global.zoomcrc.com> Passcode: 0665597535 SIP: 96641483296(a)zoomcrc.com<mailto:96641483296@zoomcrc.com> Passcode: 0665597535 ST Restricted

3 years, 9 months

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Re: OpenAMP System Reference bi-weekly

by Arnaud POULIQUEN

Hello, I will not be able to join the OpenAMP System Reference meeting this week. My update: * Rpmsg flow control RFC sent: * Linux: https://lore.kernel.org/lkml/20220520082940.2984914-1-arnaud.pouliquen@foss… * OpenAMP: https://github.com/OpenAMP/open-amp/pull/394 * OpenAMP and libmetal: zephyr integration without a fork: Received advice last week, in Zephyr discussion <https://github.com/zephyrproject-rtos/zephyr/discussions/44279> . I tested approach based on git submodule to suppress the OpenAMP libraries copy in zephyr, work fine without impact on openAMP libs. Bill also developed a solution that works. I propose to discuss approaches on discord chat or on next meeting ( Zephyr upstream scope). For short term (Dan's work integration in OpenAMP), the solution proposed by Bill is simpler to implement. As it avoids creating temporary Zephyr open-amp and libmetal modules repos in OpenAMP. Action items: * @Arnaud POULIQUEN<mailto:arnaud.pouliquen@st.com>: Set up call with Bill, Dan & Xiaomi when Dan is back in office about virtio work It seems to me that it would be better to have a pre-integration of Dan's work first and then call a meeting, to discuss the next steps. But we can have a meeting before if requested. Regards, Arnaud -----Original Appointment----- From: Nathalie Chan King Choy <nathalie(a)xilinx.com> Sent: jeudi 9 décembre 2021 19:53 To: Nathalie Chan King Choy; Arnaud POULIQUEN; Arun Balaji Kannan; Bill Mills; Milea, Danut Gabriel (Danut); etsam.anjum(a)siemens.com; jeffrey.hancock(a)siemens.com; Kumar Gala; nathalie-ckc(a)kestrel-omnitech.com; paul.sokolovsky(a)linaro.org; Stefano Stabellini; Tanmay Shah; Tom Gall; Tomas Evensen Subject: OpenAMP System Reference bi-weekly When: mercredi 25 mai 2022 09:00-10:00 (UTC-08:00) Pacific Time (US & Canada). Where: https://xilinx.zoom.us/j/96641483296?pwd=c1ZzeGNJQzR4MGdhN2FRT2VVY05WZz09&f… Note: Around the daylight/standard savings time change Europe and North America meetings get out of sync because the time change dates differ Meeting notes: https://github.com/OpenAMP/openamp-system-reference/wiki/OpenAMP-System-Ref… GitHub wiki: https://github.com/OpenAMP/openamp-system-reference/wiki GitHub repo (published stuff) : https://github.com/OpenAMP/openamp-system-reference Google Drive folder (draft stuff): https://drive.google.com/drive/folders/1dJByUkTNPOczMwB5uNUSKSf1mzQbAjQt?us… OpenAMP System Reference mailing list page: https://lists.openampproject.org/mailman/listinfo/openamp-system-reference [https://st2.zoom.us/static/5.2.3509/image/new/ZoomLogo_110_25.png]<https://zoom.us/> Hi there, Nathalie Chan King Choy is inviting you to a scheduled Zoom meeting. Join Zoom Meeting<https://xilinx.zoom.us/j/96641483296?pwd=c1ZzeGNJQzR4MGdhN2FRT2VVY05WZz09&f…> Phone one-tap: US: +19292056099,,96641483296#,,,,,,0#,,0665597535#<tel:+19292056099,,96641483296#,,,,,,0#,,0665597535#> or +16699006833,,96641483296#,,,,,,0#,,0665597535#<tel:+16699006833,,96641483296#,,,,,,0#,,0665597535#> Meeting URL: https://xilinx.zoom.us/j/96641483296?pwd=c1ZzeGNJQzR4MGdhN2FRT2VVY05WZz09&f… Meeting ID: 966 4148 3296 Passcode: u2!%S7xN@9 Join by Telephone For higher quality, dial a number based on your current location. Dial: US: +1 929 205 6099 or +1 669 900 6833 or +1 720 928 9299 or 833 548 0276 (Toll Free) or 833 548 0282 (Toll Free) or 877 853 5257 (Toll Free) or 888 475 4499 (Toll Free) India: +91 406 480 2722 or +91 446 480 2722 or +91 806 480 2722 or +91 80 71 279 440 or +91 116 480 2722 or +91 22 48 798 004 or +91 224 879 8012 or +91 226 480 2722 or +91 22 71 279 525 or 000 800 001 4002 (Toll Free) or 000 800 050 5050 (Toll Free) Ireland: +353 6 163 9031 or +353 1 536 9320 or +353 1 653 3895 or 1800 949 238 (Toll Free) or 1800 901 561 (Toll Free) or 1800 943 965 (Toll Free) Singapore: +65 3158 7288 or +65 3165 1065 or 800 852 6054 (Toll Free) or 1800 407 5602 (Toll Free) or 800 101 3814 (Toll Free) Meeting ID: 966 4148 3296 Passcode: 0665597535 International numbers<https://xilinx.zoom.us/u/arCaT7VIG> Join from a Video Conference room system Meeting ID: 966 4148 3296 Passcode: 0665597535 US: 96641483296(a)global.zoomcrc.com<mailto:96641483296@global.zoomcrc.com> Passcode: 0665597535 APAC: 96641483296(a)global.zoomcrc.com<mailto:96641483296@global.zoomcrc.com> Passcode: 0665597535 India: 96641483296(a)global.zoomcrc.com<mailto:96641483296@global.zoomcrc.com> Passcode: 0665597535 Europe: 96641483296(a)global.zoomcrc.com<mailto:96641483296@global.zoomcrc.com> Passcode: 0665597535 SIP: 96641483296(a)zoomcrc.com<mailto:96641483296@zoomcrc.com> Passcode: 0665597535 ST Restricted

3 years, 9 months

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2022-05-11 OpenAMP System Reference notes and action items

by Nathalie Chan King Choy

Hi all, Notes from today are posted at https://github.com/OpenAMP/openamp-system-reference/wiki/OpenAMP-System-Ref… Action items: * @Arnaud POULIQUEN<mailto:arnaud.pouliquen@st.com>: Set up call with Bill, Dan & Xiaomi when Dan is back in office about virtio work * @Bill Mills<mailto:bill.mills@linaro.org> prototyped implementation similar to MCU boot for Zephyr & if it works, will send PR to virtio-experiment branch at openamp & libmetal * @Bill Mills<mailto:bill.mills@linaro.org>: Need to figure out where to put DTSI stuff in CI. * @Bill Mills<mailto:bill.mills@linaro.org>: Suggest to call submission openamp-ci-builds & mark the other CI stuff obsolete. Will propose in email to TSC. * @Bill Mills<mailto:bill.mills@linaro.org> to post a link to the Google Doc into https://github.com/OpenAMP/open-amp/issues/390 Thanks & regards, Nathalie

3 years, 10 months

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Calling for agenda: 2022-05-22 OpenAMP System Reference

by Nathalie Chan King Choy

Hi all, Please let us know if you have specific topics you want to discuss on Wednesday. Here's what I collected so far: * Openamp and libmetal implementation for Zephyr: integrate similarly to MCU boot in Zephyr or branch? * Any updates on Arm's timeframe & requirements for virtio? Action items from last call: * Arnaud: To take a look at how MCU boot is integrated into Zephyr * Bill: Add Arnaud to the Arm Virtio thread & ask more Qs, clarify timeframe of H2CY22. * Bill: Publish updates to repo (just got ST part working today) * Tanmay: Write up which layers are included & which machine name & target * Arnaud: Look at Bill's repo w/ different manifests. * Tanmay: Check w/ Bruce if should sync w/ Lopper or do interim integration Thanks & regards, Nathalie

3 years, 10 months

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Openamp-system-reference