RPU subsystem can be configured in cluster-mode or split mode. Also each r5 core has separate power domains.
Signed-off-by: Tanmay Shah tanmay.shah@xilinx.com ---
Changes in v7: - None
Changes in v6: - None
Changes in v5: - Remove optional reg property from r5fss node - Move r5fss node out of axi node
Changes in v4: - Add reserved memory region node and use it in RPU subsystem node
Changes in v3: - Fix checkpatch.pl style warning
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index c715a18368c2..e8315a4f7f61 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -100,6 +100,22 @@ opp03 { }; };
+ reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rproc_0_fw_image: memory@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + + rproc_1_fw_image: memory@3ef00000 { + no-map; + reg = <0x0 0x3ef00000 0x0 0x40000>; + }; + }; + zynqmp_ipi: zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; @@ -203,6 +219,23 @@ fpga_full: fpga-full { ranges; };
+ r5fss: r5fss { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + r5f_core0: r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_0>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f_core1: r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_1>; + memory-region = <&rproc_1_fw_image>; + }; + }; + amba: axi { compatible = "simple-bus"; #address-cells = <2>;